• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    The invention relates to a method of manufacturing an electronic device (10) comprising a substrate (14) and microwires or nanowires (20) resting on the substrate, the method comprising the successive steps of covering the wires of a layer insulating layer (26), to cover the insulating layer of an opaque layer, to deposit a first layer of photosensitive resin extending on the substrate between the wires, to etch the first layer of photoresist to a first thickness by photolithography, to etching the first layer of photoresist remaining after the previous step on a second thickness by plasma etching, to burn the portion of the opaque layer not covered with the first layer of photoresist remaining after the previous step, to engrave the part of the insulating layer not covered with the opaque layer, removing the first layer of photoresist remaining after the previous step e, and remove the opaque layer.
    公开号:FR3031242A1
    申请号:FR1463372
    申请日:2014-12-29
    公开日:2016-07-01
    发明作者:Eric Pourquier；Philippe Gibert；Brigitte Martin
    申请人:Commissariat a lEnergie Atomique CEA；Aledia；Commissariat a lEnergie Atomique et aux Energies Alternatives CEA；
    IPC主号:
    专利说明:

    [0001] TECHNICAL FIELD The present invention generally relates to methods of manufacturing electronic devices comprising microwires or nanowires of semiconductor material. BACKGROUND OF THE INVENTION
    [0002] DESCRIPTION OF THE PRIOR ART Microwires or nanowires comprising a semiconductor material make it possible in particular to manufacture optoelectrical devices. By optoelectronic devices are meant devices adapted to perform the conversion of an electrical signal into an electromagnetic radiation or vice versa, and in particular devices dedicated to the detection, measurement or emission of electromagnetic radiation or devices dedicated to photovoltaic applications. For certain structures in which the nanowires or microwires are formed on a support, it is necessary to cover with an insulating layer the lower portion of each nanowire or microfil as well as the support between the nanowires or microwires, the upper portion of each nanowire or microfilament not being covered by this insulating layer. However, it may be difficult to achieve uniform insulation of the feet of a set of nanowires or microwires, in particular 3031242 B13815 - DD15984JBD 2 to isolate the lower portion of each nanowire or microfil of a height that is substantially the same for all microfilts and nanowires. SUMMARY Thus, an object of an embodiment is to overcome at least in part the disadvantages of the methods of manufacturing the electron microwire or nanowire devices described above. Another object of one embodiment is that the insulation heights of the lower portions of nanowires or microwires of a set of nanowires or microwires are substantially equal. Another object of an embodiment is that the electronic device can be formed on an industrial scale and at low cost. Thus, an embodiment provides a method of manufacturing an electronic device comprising a substrate and microwires or nanowires resting on the substrate, the method comprising the following successive steps: a) covering the microfilts or nanowires with an insulating layer ; b) covering the insulating layer with an opaque layer; c) depositing a first layer of photosensitive resin extending on the substrate between the wires; d) etching the first photoresist layer on a first thickness by photolithography; e) etching the first layer of photoresist remaining after step d) on a second thickness by plasma etching; f) etching the portion of the uncoated opaque layer of the first photoresist layer remaining after step e); g) etching the part of the insulating layer not covered with the opaque layer; (H) removing the first layer of photoresist remaining after step e); and i) removing the opaque layer. According to one embodiment, the height of the microfilms 5 or nanowires is between 250 nm and 50 pin. According to one embodiment, the maximum thickness of the first photoresist layer in step c) is greater than the height of the microwires or nanowires. According to one embodiment, the thickness of the insulating layer is between 5 nm and 1 gm. According to one embodiment, the plasma etching is an oxygen plasma etching. According to one embodiment, the opaque layer is made of a metal or a metal alloy.
    [0003] According to one embodiment, the thickness of the opaque layer is between 5 nm and 1 μm. According to one embodiment, the method further comprises the following successive steps after step i): j) forming a shell on the portion of each microfil or nanowire not covered with the insulating layer, the shell comprising a region active sensor adapted to capture or emit the majority of the radiation supplied or picked up by the electronic device; k) forming an electrode layer on the shells and on the insulating layer; 1) covering the electrode layer with a conductive layer; m) depositing a second layer of photoresist extending over the conductive layer between the wires; N) delineating in the second resin layer, by photolithography, a block of resin extending between the microwires or nanowires; o) etching the resin block on a third thickness by plasma etching; P) etching the portion of the second uncovered conductive and reflective layer of the photoresist block remaining after step o); and q) removing the second photoresist layer 5 remaining after step o). According to one embodiment, step n) comprises the following steps: r) partially exposing the second layer of photoresist to a fourth thickness; S) irradiating portions of the second photoresist layer throughout its thickness using a blackout screen; and t) etching the portions of the second layer of photosensitive resin insolated in steps r) and s).
    [0004] According to one embodiment, the conductive layer is reflective. BRIEF DESCRIPTION OF THE DRAWINGS These and other features and advantages will be set forth in detail in the following description of particular embodiments in a non-limiting manner with reference to the accompanying figures, in which: FIG. partial and schematic, of an embodiment of an optoelectronic device with microwires or nanowires; and FIGS. 2A to 2P are partial and schematic sections of structures obtained at successive stages of an embodiment according to the invention of a method of manufacturing the optoelectronic device of FIG. 1. DETAILED DESCRIPTION For the sake of clarity, the same elements have been designated by the same references in the various figures and, moreover, as is customary in the representation of the electronic circuits, the various figures are not drawn to scale. In addition, only the elements useful for understanding the present description have been shown and are described.
    [0005] In particular, the polarization and control means of the optoelectronic device are well known and are not described. In the remainder of the description, unless otherwise indicated, the terms "substantially", "about" and "of the order 5 of" mean "to within 10%", preferably to within 5%. The present application relates in particular to electronic devices with a three-dimensional structure comprising three-dimensional elements, for example microwires, nanowires, conical elements or frustoconical elements. In particular, a conical or frustoconical element may be a conical or frustoconical element of revolution or a conical or frustoconical pyramidal element. In the remainder of the description, embodiments are described in particular for electronic devices with a three-dimensional structure with microfilts or nanowires. However, these embodiments may be implemented for three-dimensional elements other than microfilms or nanowires, for example three-dimensional conical or frustoconical elements. The term "microfilar", "nanowire", "conical element" or "frusto-conical element" denotes a three-dimensional structure of elongate shape in a preferred direction of which at least two dimensions, called minor dimensions, are between 5 nm and 2.5 pin, preferably between 50 nm and 2.5 μm, the third dimension, called major dimension, being greater than or equal to 1 time, preferably greater than or equal to 5 times and even more preferably greater than or equal to 10 times, the larger of the minor dimensions. In some embodiments, the minor dimensions may be less than or equal to about 1 μm, preferably from 100 nm to 1 μm, more preferably from 100 nm to 800 nm. In some embodiments, the height of each microfil or nanowire may be greater than or equal to 500 nm, preferably between 1 μm and 50 μm. In the remainder of the description, the term "wire" is used to mean "microfil or nanowire". Preferably, the average line of the wire which passes through the barycenters of the straight sections, in planes perpendicular to the preferred direction of the wire, is substantially rectilinear and is hereinafter referred to as the "axis" of the wire. BRIEF DESCRIPTION OF THE DRAWINGS
    [0006] In the remainder of the description, embodiments will be described in the case of an optoelectronic device with light-emitting diodes. However, it is clear that these embodiments may relate to other applications, including devices dedicated to the detection or measurement of electromagnetic radiation or devices dedicated to photovoltaic applications. FIG. 1 is a partial and schematic cross section of an optoelectronic device 10 made from wires as described above and adapted to the emission of electromagnetic radiation. The device 10 comprises, from the bottom upwards in FIG. 1: a first polarization electrode 12; a substrate 14, for example a semiconductor, comprising parallel faces 16 and 18, the face 16 being in contact with the electrode 12 and the face 18 being able to be treated so as to promote the growth of wires in an organized manner, this treatment being able to understanding the formation of a layer, not shown, on the surface of the substrate 14; Wires 20 of axis A (three wires being shown), of height H1, each wire comprising a lower portion 22 of height H2, in contact with the face 18, and an upper portion 24 of height H3; an insulating layer 26 covering the periphery of a portion of each lower portion 22 and covering the substrate 14 between the wires 20; a shell 28 covering each upper portion 24; a second electrode layer 30 covering the shells 28 and the insulating layer 26; and a conductive portion 32 covering the second electrode layer 30 between the wires 20, and possibly extending over a portion of the lower portion 22 of each wire 20, but not extending over the upper portion. 24 of each wire 20. Each wire 20 is, at least in part, formed from at least one semiconductor material. According to one embodiment, the semiconductor material is selected from the group consisting of compounds III-V, compounds II-VI or semiconductors or compounds of group IV. The assembly formed by each wire 20 and the associated shell 28 constitutes a light-emitting diode. The shell 28 comprises in particular an active zone which is the layer from which the majority of the electromagnetic radiation supplied by the light-emitting diode is emitted. According to one example, the active zone may comprise confinement means such as multiple quantum wells. In the present embodiment, at least some light-emitting diodes have common electrodes and when a voltage is applied between the electrodes 12 and 30, light radiation is emitted from the active areas of these light-emitting diodes. The light-emitting diodes of the optoelectronic device 10 may be divided into one set, two or more sets of two sets of light-emitting diodes. Each set may include a few light emitting diodes with several million light emitting diodes. In the present embodiment, the insulating layer 26 delimits the shell 28 for each wire 20 and provides electrical insulation between the electrode layer 30 and the substrate 14. In the present embodiment, the conductive portion 32 advantageously allows the resistance of the electrode layer 30 to be reduced. Preferably, the conductive portion 32 is reflective and advantageously makes it possible to increase the proportion of the radiation emitted by the electrodes 30. LEDs which escape from the optoelectronic device 10. FIGS. 2A to 2P are partial and schematic sections, structures obtained at successive stages of an embodiment of a method of manufacturing the optoelectronic device 10 shown in FIG. Figure 1. Figure 2A shows the structure obtained after growing the wires 20 on the substrate 14.
    [0007] The substrate 14 may correspond to a one-piece structure or may correspond to a layer covering a support made of another material. The substrate 14 is preferably a semiconductor substrate, for example a silicon, germanium, silicon carbide, III-V compound, such as GaN or GaAs, or a ZnO substrate, or a substrate. conductor, for example a substrate made of a metal or a metal alloy, in particular copper, titanium, molybdenum and steel. Preferably, the substrate 14 is a monocrystalline silicon substrate. Preferably, it is a semiconductor substrate compatible with the manufacturing processes used in microelectronics. The substrate 14 may correspond to a multilayer structure of silicon on insulator type, also called SOI (acronym for Silicon On Insulator). In this case, the electrode 12 can be made on the side of the face 18 of the substrate 14. The substrate 14 can be heavily doped, weakly doped or undoped. Pretreatment of substrate 14 to promote growth of yarns at preferred locations may be provided. The treatment applied to the substrate to promote the growth of threads may correspond to one of the treatments described in the documents US Pat. No. 7,829,443, FR 2,995,729 or FR 2,997,558. The threads may be, at least in part, formed from semiconductor materials predominantly comprising a III-V compound, for example a III-N compound. Examples of group III elements include gallium (Ga), indium (In) or aluminum (Al). Examples of III-N compounds are GaN, AlN, InN, InGaN, AlGaN or AlInGaN. Other Group V elements may also be used, for example, phosphorus or arsenic. In general, the elements in compound III-V can be combined with different mole fractions. The wires 20 may be, at least in part, formed from semiconductor materials predominantly comprising a II-VI compound. Examples of group II elements include elements of the HA group, especially beryllium (Be) and magnesium (Mg) and elements of group IIB, especially zinc (Zn), cadmium (Cd) and mercury. (Hg). Examples of Group VI elements include elements of the VIA group, including oxygen (O) and tellurium (Te). Examples of compounds II-VI are ZnO, ZhMgO, CdZnO, CdZhMgO, CdHgTe, CdTe or HgTe. In general, the elements in II-VI can be combined with different mole fractions. The wires 20 may be, at least in part, formed from semiconductor materials having predominantly at least one Group IV element. Examples of group IV semiconductor materials are silicon (Si), carbon (C), germanium (Ge), silicon carbide (SiC) alloys, silicon-germanium (SiGe) alloys or carbide alloys of germanium (GeC).
    [0008] The height H1 of each wire 20 may be between 250 nm and 50 μm, preferably between 1 μm and 20 μm. Each wire 20 may have an elongated semiconductor structure along an axis substantially perpendicular to the face 18. Each wire 20 may have a generally cylindrical shape. The axes of two adjacent yarns may be from 0.5 μm to 20 μm and preferably from 3 μm to 20 μm. For example, the son 20 may be regularly distributed, in particular according to a hexagonal or square network. The cross section of the yarns 20 may have different shapes, such as, for example, an oval, circular or polygonal shape, such as triangular, rectangular, square or hexagonal shape. Thus, it is understood that when the "diameter" in a cross-section of a wire or a layer deposited on this wire is mentioned here, it is a quantity associated with the surface 5 of the structure referred to in FIG. this cross section, corresponding, for example, to the diameter of the disk having the same surface as the cross section of the wire. The average diameter of each wire 20 may be between 50 nm and 10 μm, preferably between 200 nm and 10 μm.
    [0009] The yarn growth process may be a chemical vapor deposition (CVD) method or an organometallic chemical vapor deposition (MOCVD), also known as a chemical vapor deposition (VOC) method. known as organometallic vapor phase epitaxy (or MOVPE), which is the acronym for Metal-Organic Vapor Phase Epitaxy. However, processes such as molecular beam epitaxy (MBE), gas-source MBE (MBBE), organometallic MBE (MOMBE), plasma-assisted MBE (PAMBE), Atomic Layer Epitaxy (ALE) or hydride vapor phase epitaxy (HVPE) can be used. In addition, electrochemical processes may also be used, for example, chemical bath deposition (CBD), hydrothermal processes (also known as hydrothermal processes), liquid aerosol pyrolysis or electrodeposition. By way of example, the process may comprise injecting into a reactor a precursor of a Group III element and a precursor of a Group V element. Examples of precursors of group elements III are trimethylgallium (TMGa), triethylgallium (TEGa), trimethylindium (TMIn) or trimethylaluminum (TMA1). Examples of group V precursors are ammonia, tertiarybutylphosphine (TBT), arsine (AsH3) or dimethylhydrazine (UDMH). FIG. 2B shows the structure obtained after having deposited the insulating layer 26 on all the wires 20 and on the face 18 between the wires. The insulating layer 26 may be of a dielectric material, for example silicon oxide (SiO2), silicon nitride (SixNy, where x is approximately equal to 3 and y is approximately equal to 4, for example Si3N4), silicon oxynitride (in particular of general formula SiOxNy, for example Si2ON2), hafnium oxide (HfO2), aluminum oxide (Al2O3) or diamond. For example, the thickness of the insulating layer 26 is between 5 nm and 1 pin, preferably between 10 nm and 500 nm, for example equal to about 300 nm. The insulating layer 26 may be deposited by way of example by plasma chemical vapor deposition (PECVD), a low-pressure chemical vapor deposition (LPCVD) known as Low-Pressure Chemical Vapor Deposition (LPCVD). Pressure Chemical Vapor Deposition), chemical vapor deposition under sub-atmospheric pressure (SACVD), CVD, Physical Vapor Deposition (PVD), or Atomic Layer Deposition (ALD). FIG. 2C shows the structure obtained after having deposited an opaque layer 40 on the insulating layer 26. The opaque layer 40 may be made of a metal or a metal alloy, for example aluminum (Al), titanium (Ti ), copper (Cu), an alloy of aluminum and silicon, or tungsten (W). The thickness of the opaque layer 40 may be between 50 nm and 1 μm, preferably between 100 nm and 200 nm, for example equal to about 150 nm. The opaque layer 40 is, for example, deposited by PVD, CVD or ALD. FIG. 2D shows the structure obtained after having deposited a layer 42 of a photoresist on the whole of the structure. The resin layer 42 is in particular present between the wires 20. The maximum thickness of the resin layer 42 is greater than the height H1 of the wires 20. The maximum thickness of the resin layer 42 is included in FIGS. between 250 nm and 50 pin. Figure 2E shows the structure obtained after a first step of partially etching the resin layer 42 in which only an upper portion of the resin layer 42 is removed. The thickness removed from the resin layer 42 after the first etching step may be a few micrometers. The first etching step is preferably a photolithography step comprising a step of insulating the resin layer 42, for example by exposing the resin layer 42 to ultraviolet radiation, and a step of developing the photolithography step. resin layer in which a portion of the resin layer is removed, for example by liquid etching, by contacting the resin with a developer. The photosensitive resin may be a positive photosensitive resin, i.e. the portion of the photosensitive resin exposed to suitable radiation becomes soluble to the developer and the unexposed photosensitive resin portion remains insoluble. Partial insolation and development of the resin, in particular by adjustment of the insolation energy and / or the insolation time, can then be implemented. The energy of the radiation may be for example between 20 and 100 mW / cm 2. The duration of insolation is, for example, between about 25 seconds and a hundred seconds. The photosensitive resin may be a negative photosensitive resin, i.e., the portion of the photosensitive resin exposed to suitable radiation becomes insoluble to the developer and the unexposed photosensitive resin portion remains soluble. In this case, partial development of the resin by adjusting the development time can be carried out without exposure of the resin or with post-development exposure. According to one embodiment, the son 20 may be at least partially transparent. The presence of the opaque layer 40 then makes it possible to reduce, or even eliminate, the guiding of the insolation radiation by the wires 20, which can lead to undesirable overexposure of regions of the resin layer 40 around 20 FIG. 2F shows the structure obtained after a second etching step of the resin layer 42 in which the resin layer 42 is again etched in a partial manner, only an upper portion of the resin layer 42 obtained at the end of the previous step being removed. The thickness removed from the resin layer 42 after the second etching step may be from a few hundred nanometers to a few micrometers. The second etching step is preferably an etching step using an oxygen-based plasma. According to one embodiment, it may be used for the plasma etching method according to the invention any conventional etching source such as RIE (Reactive Ion Etching) sources and high density plasma, in particular any source of engraving of the type used for etching organic materials. The excitation power can be between 10 W to 1 kW. The substrate can be maintained at room temperature, for example at 20 ° C. The use of a plasma etching advantageously makes it possible to reach the desired height in a precise and reproducible manner for the resin layer 42. In addition, the use of a plasma enables the surfaces to be cleaned. exposed for subsequent steps, including removing unwanted organic residues. This also makes it possible to avoid the parasitic effects which occur during the exposure of a photolithography because of the shape of the wires and layers present and in particular resulting in a narrowing of the resin strips (in English notching ). FIG. 2G shows the structure obtained after a step of etching the portion of the opaque layer 40 not covered by the resin layer 42 and a step of etching the portion of the insulating layer 26 which is then no longer covered by the opaque layer 40. The etching of the opaque layer 40 may be a wet etching or a dry etching (plasma etching). The etching of the insulating layer 26 may be a wet etching or a dry etching (plasma etching). Preferably, these etchings are selective with respect to the resin.
    [0010] Figure 2H shows the structure obtained after a step of removing the remaining resin layer. The removal of the remaining resin layer can be achieved by dipping the structure shown in FIG. 2G in a bath containing a solvent suitable for dissolving the resin layer 42.
    [0011] FIG. 21 represents the structure obtained after an etching step of the opaque layer 40. The etching may be a wet etching or a dry etching (plasma etching) and selective with respect to the wires 20 and with respect to the layer 26. The steps 2J to 2P to be described are suitable for the formation of the structure shown in Figure 1. In general, the subsequent steps of the process will depend on the intended application. FIG. 2J shows the structure obtained after the following steps: formation of the shell 28 for each wire 20, for example by MOCVD; forming the first electrode 30 for example by MOCVD, ALD, PVD, CVD or PECVD; and forming a conductive layer 44 overlying the first electrode 30, for example by PVD, ALD, CVD or vacuum evaporation. The electrode 30 is adapted to polarize the active zone of the shell 28 covering each wire 20 and to let the electromagnetic radiation emitted by the electroluminescent diodes pass through. The material forming the electrode 30 may be a transparent and conductive material such as indium tin oxide (ITO), zinc oxide which may or may not be doped with aluminum. , or gallium or boron, or graphene. By way of example, the electrode layer 30 has a thickness of between 20 nm and 500 nm, preferably between 100 nm and 200 nm. The conductive layer 44 may correspond to a metal layer, for example aluminum, silver, copper, gold or ruthenium or an alloy of at least two of these compounds. For example, the conductive layer 44 has a thickness between 100 nm and 2000 nm. Preferably, the layer 44 is reflective. FIG. 2K shows the structure obtained after having deposited a layer 46 of a photoresist on the entire structure. The resin layer 46 is in particular present between the wires 20. The maximum thickness of the resin layer 46 is preferably greater than the height of the wires 20 covered with the shells 28, the electrode layer 30 and the Conductive layer 44. The maximum thickness of the resin layer 46 is between 250 nm and 50 μm. The resin layer 46 may have the same composition as the resin layer 42. Figure 2L shows the structure obtained after a first partial insolation of the resin layer 46 in which only an upper portion of the resin layer 46 is exposed. and a second partial insolation of the resin layer 46, in particular by using an occulting screen. The two insolation steps lead to insolating the entire resin layer 46 with the exception of a resin block 48 which extends over the layer 44 between the wires 20 only over a portion of the height of the wires. 20. In FIG. 2L, a hatched area 471 represents the upper portion of the resin layer 46 exposed during the first exposure step and is represented by a shaded area 472 the additional portion of the resin layer 30. 46 exposed during the second stage of insolation. FIG. 2M represents the structure obtained after an etching step which leads to the obtaining of the resin block 48. The etching is preferably a step of development of the resin layer 46 of a photolithography process.
    [0012] Figure 2N shows the structure obtained after a second step of etching the resin block 48 in which only an upper portion of the resin block 48 is removed. This step can be performed by plasma etching as previously described in connection with FIG. 2F for the second etching step of the resin layer 42. FIG. 20 represents the structure obtained after a step of etching the portion of the conductive layer 44 not covered by the resin block 48. The conductive portion 32 10 is thus obtained. The etching of the conductive layer 44 may be a wet etching or a dry etching (plasma etching). Preferably, this etching is selective with respect to the resin and with respect to the layer 30. FIG. 2P shows the structure obtained after a step of removing the resin block 48.
    权利要求:
    Claims (10)
    [0001]
    REVENDICATIONS1. A method of manufacturing an electronic device (10) comprising a substrate (14) and microwires or nanowires (20) resting on the substrate, the method comprising the following successive steps: a) covering the microfilms or nanowires with an insulating layer (26); b) covering the insulating layer with an opaque layer (40); c) depositing a first layer of photoresist (42) extending on the substrate between the wires; d) etching the first photoresist layer on a first thickness by photolithography; e) etching the first photoresist layer remaining after step d) on a second thickness by plasma etching; f) etching the portion of the uncoated opaque layer of the first photoresist layer remaining after step e); g) etching the portion of the uncoated insulating layer 20 of the opaque layer; h) removing the first photoresist layer remaining after step e); and i) removing the opaque layer.
    [0002]
    The method of claim 1, wherein the height of the microwires or nanowires (20) is between 250 nm and 50 μm.
    [0003]
    The method of claim 1 or 2, wherein the maximum thickness of the first photoresist layer (42) in step c) is greater than the height of the microwires or nanowires (20).
    [0004]
    4. Method according to any one of claims 1 to 3, wherein the thickness of the insulating layer (26) is between 5 nm and 1 gm. 3031242 B13815 - DD15984JBD 18
    [0005]
    The method of any one of claims 1 to 4, wherein the plasma etching is oxygen plasma etching.
    [0006]
    The method of any one of claims 1 to 5, wherein the opaque layer (40) is a metal or a metal alloy.
    [0007]
    The method of any one of claims 1 to 6, wherein the thickness of the opaque layer (40) is between 5 nm and 1 pin. 10
    [0008]
    The process according to any one of claims 1 to 7, further comprising the following successive steps after step i): j) forming a shell (28) on the portion of each microfil or nanowire (20) no covered with the insulating layer (26), the shell comprising an active region adapted to capture or emit the majority of the radiation supplied or captured by the electronic device; k) forming an electrode layer (30) on the shells and on the insulating layer; 1) covering the electrode layer with a conductive layer (44); m) depositing a second photoresist layer (46) extending over the conductive layer between the wires; n) delineating in the second resin layer, by photolithography, a resin block (48) extending between the microwires or nanowires (20); o) etching the resin block on a third thickness by plasma etching; p) etching the portion of the second non-coated conductive and reflective layer 30 of the photoresist block remaining after step o); and q) removing the second photoresist layer remaining after step o).
    [0009]
    The method of claim 8, wherein step n) comprises the following steps: r) partially exposing the second photoresist layer (46) to a fourth thickness; s) irradiating portions of the second photoresist layer throughout its thickness using a blackout screen; and t) etching the portions of the second layer of photosensitive resin insolated in steps r) and s).
    [0010]
    The method of claim 8 or 9, wherein the conductive layer (44) is reflective.
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    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    WO2014064276A1|2012-10-26|2014-05-01|Aledia|Optoelectric device and method for manufacturing the same|
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    WO2014196920A1|2013-06-05|2014-12-11|Sol Voltaics Ab|A solar cell structure and a method of its fabrication|WO2020183090A1|2019-03-12|2020-09-17|Commissariat A L'energie Atomique Et Aux Energies Alternatives|Method for coating chips|FR1463372A|1965-01-11|1966-12-23|Internal combustion engine with rotary piston|
    KR20150052343A|2007-01-12|2015-05-13|큐나노 에이비|Nitride nanowires and method of producing such|
    WO2010062644A2|2008-10-28|2010-06-03|The Regents Of The University Of California|Vertical group iii-v nanowires on si, heterostructures, flexible arrays and fabrication|
    FR2995729B1|2012-09-18|2016-01-01|Aledia|SEMICONDUCTOR MICROFILL OR NANOWILE OPTOELECTRIC DEVICE AND METHOD FOR MANUFACTURING THE SAME|
    US9500519B2|2012-12-03|2016-11-22|Yale University|Superconducting single photon detector|
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    FR1463372A|FR3031242B1|2014-12-29|2014-12-29|METHOD FOR MANUFACTURING ISOLATED FOOT SEMICONDUCTOR NANOWIRS OR MICROFILES|FR1463372A| FR3031242B1|2014-12-29|2014-12-29|METHOD FOR MANUFACTURING ISOLATED FOOT SEMICONDUCTOR NANOWIRS OR MICROFILES|
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    PCT/FR2015/053758| WO2016108023A1|2014-12-29|2015-12-24|Process for fabricating semiconductor nanowires or microwires having insulated roots|
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